The present invention relates to a semiconductor memory array and, more particularly, to a layout method of the semiconductor memory array. Memory elements or cells of the semiconductor memory device are influenced by the problems which are caused by the layout of more densely packed cells of the memory array, because the semiconductor memory device tends to higher and higher packing of the cells of a memory circuit in a minute chip area.
Particularly, in a memory cell array having a plurality of bit lines and a plurality of word lines, the narrower pitch between the lines because of its tendency to higher packing of cells of the circuit, brings about capacitive couplings between the lines when a signal is transmitted through a line. The capacitive coupling between the lines is doubled by the capacitive component of the line itself.
The larger the capacity of the semiconductor memory device, the longer the length of the word line, and the narrower the pitch between the word lines.
However, since the time required to access the memory cell depends upon the length of the word line, the longer word line is undesirable. In general, to compensate for the access time delay, a metal layer is formed on polysilicon which is the matter of the word line, so that high speed operation has been possible. However, coating the word lines with the metal causes the capacitive coupling between the lines to be larger due to the narrower pitch between the lines. Moreover, noise due to capacitive coupling between the metals is generated. Because the noise due to the capacitive coupling between the word lines is charged or discharged when one word line is selected, it is impossible to guide a correct memory operation in high speed.
Of course, since a semiconductor device incorporating miniaturization of the metal oxide semiconductor transistor cell and minutely scaled layout of the memory array according to higher packing of the cells of the memory circuit has a high level driving voltage to drive the word lines, it is unable to neglect the noise due to the high level driving voltage. Therefore, if the method of lowering the driving voltage to drive the word line to less than 5 volts is adopted in order to remove this noise, a problem exists in that the transistor requires its own threshold voltage to be operated.
On the other hand, another problem caused by the higher packing of cells of the memory circuit is that since the row address decoders selecting one bit line among a plurality of bit lines are arranged in the limited memory area, the fabrication process of the transistor and the layout of the memory array is difficult.
Particularly, in a semiconductor memory device having a plurality of decoders, the more complicated the memory array is, the more increased the number of strapping lines, and the greater the number of the signal lines.
The word line driver applies the driving voltage for selecting a given word line to the correspondent word line, the driver being supplied with an address signal from the row address decoder. Therefore, as described above, as the pitch between the word lines becomes more narrow, arranging the word line drivers in the limited memory area is more difficult.
The conventional memory array; having several problems as described above, is illustrated in FIG. 1. Referring to FIG. 1, the array includes a plurality of bit lines BL.sub.1 -BL.sub.j, and a plurality of word lines arranged across the bit lines, and word drivers 1 coupled to the word lines arranged on one side of the memory array. The memory cells are arranged on the crossing points of the word lines and the bit lines, the memory of the present invention has folded bit lines. In read operation of the memory device, the information being stored in the cell selected by the word line is loaded on the selected bit line, and then the sense amplifier selected by the bit line reads the information. At this time, the coupling capacitance between the selected word line and the neighboring word line is illustrated in FIG. 3A. Referring to FIG. 3A, capacitive components will be described according to the memory array of FIG. 1.
Coupling capacitances C.sub.12, C.sub.23, C.sub.34, C.sub.45 between the word lines WL.sub.1 -WL.sub.4, and substrate capacitances C.sub.1, C.sub.2, C.sub.3, C.sub.4 of the word lines WL.sub.1 -WL.sub.4 are presented. Therefore, when any word line is selected, the voltage of word line coupling noise is: ##EQU1## (V.sub.CP : voltage of word line coupling noise V.sub.WL : driving voltage of selected word line
Cs: substrate capacitance of word line PA1 Cc: coupling capacitance)
The substrate capacitance Cs of the word line depends on the metal formation of the word line and on the characteristics of the substrate, so that the substrate capacitance Cs may be regarded as the constant. The driving voltage V.sub.WL of the word line is the factor to effect the word line coupling noise, but since the driving voltage for driving the word line is, at most, equal to the threshold voltage of the memory cell transistor, the term V.sub.WL is neglectable. Therefore, it can be easily understood by one skilled in the art that the important factor to effect the word line coupling noise is the coupling capacitance Cc.